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Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes
SYSC5603 (ELG6163) Digital Signal Processing Microprocessors, Software and Applications
Miodrag Bolic
1
Outline
FIR filter on ADPS-21x
DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
2
ADSP -21x
Copied from [Kester03]
3
CALCULATING OUTPUTS OF 4-TAP FIR FILTER USING A CIRCULAR BUFFER
y(3) = h(0) x(3) + h(1) x(2) + h(2) x(1) + h(3) x(0)
y(4) = h(0) x(4) + h(1) x(3) + h(2) x(2) + h(3) x(1)
y(5) = h(0) x(5) + h(1) x(4) + h(2) x(3) + h(3) x(2)
Memory
Location
 

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